1. Field of the Invention
The present invention relates to "power on clear" circuit which sets or resets memory elements, such as flip-flop circuits in an integrated circuit to, a predetermined state when the power supply is turned on.
2. Description of the Prior Art
Integrated circuits consist of various circuit elements such as gates, flip-flop circuits, and the like. Among them, elements such as flip-flop circuits, which will stably assume a given state among a plurality of states, must reliably acquire a set state when they are set or a reset state when they are reset at the time when the power supply is turned on, i.e., at the time when the operation is started. Such an initial state can be set by feeding a set signal or a reset signal from an external unit. In this case, however, the number of pins of the integrated circuit is increased by one as a matter of course. Therefore, it has been proposed to provide the integrated circuit with a circuit which generates the set or reset signal when the power supply is turned on.
An example of a power on clear circuit has been disclosed in the specification of Japanese patent application No. 127242/77 that was filed in Japan. The above circuit consists, as shown in FIG. 1, of p-channel field effect transistors Q.sub.1 and Q.sub.2, which are connected in series, and a resistor R and an n-channel field effect transistor Q.sub.3, which are connected in series, wherein the gates and sources of each of the transistors Q.sub.1 and Q.sub.2 are short-circuited, a terminal or connection point P.sub.2 between the transistor Q.sub.1 and the transistor Q.sub.2 is connected to the gate of the transistor Q.sub.3, the drain of the transistor Q.sub.1 and one end of the resistor R are connected to a high-potential source V.sub.DD, the sources of the transistors Q.sub.2 and Q.sub.3 are connected to a low-potential source V.sub.SS, and an output pulse is obtained from a terminal or connection point P.sub.1 between the resistor R and the transistor Q.sub.3. According to the abovementioned conventional circuit, when the potential of the source V.sub.DD starts to rise after being turned on, the potential at point P.sub.1 is raised as this point is interlocked to the potential V.sub.DD through the resistor R, while at the same time stray capacitors are being electrically charged. As the potential V.sub.DD reaches a threshold voltage Vth of, for example, 1 volt, the transistor Q.sub.1 is rendered conductive, and the gate potential of the transistor Q.sub.3 starts to rise. As the gate potential reaches the threshold voltage Vth, the transistor Q.sub.3 is rendered conductive, and the potential at the output terminal decreases. Thus, a voltage having the waveform of a mountain is obtained and is shaped to produce a clear signal for the flip-flop circuits. The above circuit generates a clear signal during the interval between the time when the potential P.sub.1 is raised by the resistor R and the time when the potential at P.sub.1 is lowered by the transistors Q.sub.1, Q.sub.3. Therefore, a sufficient time interval can be obtained to produce a clear signal of the desired pulse width when the potential of the power source V.sub.DD rises relatively slowly. When the voltage V.sub.DD rises quickly, however, the time difference becomes small, and the width of the clear pulse becomes so narrow that it is difficult to guarantee reliable operation. With this circuit, furthermore, the transistors Q.sub.1 to Q.sub.3 are all rendered conductive when the power supply is turned on; electric current is consumed at all times by the transistors Q.sub.1, Q.sub.2, Q.sub.3 and by the resistor R. One advantage of a CMOS chip is that no current is permitted to flow during the above rest state. With the power on clear circuit, however, a constant current flows at all times.